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Power Design India - total search 13 articles sort by date sort by relevance
I/O gating versus sleep modes 2006-09-20
Here are the differences between CPLDs with an I/O gating feature, and the "sleep modes" used by FPGAs  
Using CPLDs to manage power consumption in portables 2006-09-26
This article discusses two methods for reducing an application's power consumption through CPLDs.  
Improving battery life with ultra low-power codecs 2009-08-10
Here's how you can improve portable consumer electronic devices' battery life by employing ultra low-power codecs.  
PI-IPM cuts motor drive design time, risk 2003-08-18
power  
LDB-based buck converters for MPU multiphase interleaving 2007-06-26
The article describes how to implement a multiphase control system with a higher gain bandwidth product to keep system output voltage stable and well regulated during load transients.  
Perform fault monitoring, manage backplane power 2004-09-16
Perform fault monitoring, manage backplane power  
Delta-Sigma ADCs 2004-10-25
Delta-Sigma ADCs  
VIPower makes easier PFC converters 2003-11-03
Since January 2001, the Euro-  
Choose right: Low-power PLDs for portables 2008-06-26
Utilise the key features of low-power PLDs for real power and cost savings.  
Cutting power consumption with low-power CPLD 2010-04-15
Any engineer involved with portable or handheld products knows that minimizing power consumption is a requirement for today's designs.  
Power-Sensitive Design Techniques On FPGA Devices 2001-07-03
Power-Sensitive Design Techniques On FPGA Devices  
Modified LDO regulator sinks PECL-termination current 2008-09-12
For high-speed clock and data systems, PECL is emerging as a preferred alternative to single-ended CMOS and TTL logic.  
PolyPhase for step-up conversion 2005-05-02
The benefits of PolyPhase operation are now available for high-power step-up conversion. Read more  


 
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